1. Field of the Invention
The present invention relates to a track and hold circuit scheme, and more particularly, to a high-speed open-loop track and hold circuit with high linearity.
2. Description of the Prior Art
In an analog-to-digital converter (ADC), a high-speed track and hold circuit is one of the essential elements. The high-speed track and hold circuit in the prior art is realized by an open-loop scheme. Please refer to FIG. 1. FIG. 1 shows a diagram of a track and hold circuit 100 of a conventional open-loop scheme. As shown in FIG. 1, the track and hold circuit 100 is composed of a sampling network (which comprises a switch 110 and a capacitor 120), a source follower 130, and a current source 140. When the switch device 110 is turned on, the output voltage Vo will track the input voltage Vi, and when the switch device 110 is turned off, the input voltage Vi at that instance will be stored in the capacitor 120. After a settling time period, the output voltage Vo will catch up with the voltage value stored in the capacitor 120, and then remain unchanged. Although this scheme exhibits high-speed properties, the linearity of the transfer function of the source follower 130 will be adversely affected by the body effect and the channel length modulation effect, and consequently performance will decline significantly.
Please refer to FIG. 2. FIG. 2 shows a diagram of a track and hold circuit 200 of another conventional open-loop scheme. In the track and hold circuit 200, the source follower 230 is implemented using a MOS transistor with a well structure, such as an NMOS transistor with a deep N well structure, or a PMOS transistor with an N well structure. As shown in FIG. 2, the source follower 230 has a body terminal coupled to its source terminal and a current source 240, so as to eliminate the above-mentioned body effect. However, there will be parasitic capacitance generated at the PN junction, and the tracking speed of the track and hold circuit 200 will be reduced due to the existence of the parasitic capacitance loading. In addition, the linearity of the source follower 230 in the track and hold circuit 200 will also be affected by the channel length modulation effect and performance will decline greatly.